D A T A
S H E E T
AC CHARACTERISTICS
t
WC
Addresses
Valid PA
t
RC
Valid RA
t
WC
Valid PA
t
WC
Valid PA
t
AH
t
ACC
CE#
t
CE
t
OE
OE#
t
OEH
t
WP
WE#
t
WPH
t
DS
t
DH
Data
Valid
In
t
CPH
t
CP
t
GHWL
t
DF
t
OH
Valid
Out
Valid
In
Valid
In
t
SR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
Figure 20.
Back-to-back Read/Write Cycle Timings
t
RC
Addresses
VA
t
ACC
t
CE
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ7
High Z
VA
VA
t
OE
t
DF
Complement
Complement
True
Valid Data
High Z
DQ0–DQ6
t
BUSY
RY/BY#
Status Data
Status Data
True
Valid Data
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 21. Data# Polling Timings (During Embedded Algorithms)
44
Am29DL32xG
25686B10 December 4, 2006