D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
t
AS
t
WC
Addresses
555h
PA
t
AH
CE#
OE#
t
WP
WE#
t
CS
t
DS
Data
t
DH
PD
Status
D
OUT
t
WPH
t
WHWH1
Read Status Data (last two cycles)
PA
PA
t
CH
A0h
t
VCS
V
CC
Note:
PA = program address, PD = program data, D
OUT
is the true data at the program address.
Figure 9.
Program Operation Timings
Erase Command Sequence (last two cycles)
t
AS
t
WC
Addresses
2AAh
SA
555h for chip erase
Read Status Data
VA
VA
t
AH
CE#
OE#
t
WP
WE#
t
CS
t
DS
t
CH
t
WPH
t
WHWH2
t
DH
Data
55h
30h
10 for Chip Erase
In
Progress
Complete
t
VCS
V
CC
Note:
SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 10.
Chip/Sector Erase Operation Timings
October 31, 2006 Am29F010B_00_C7
Am29F010B
23
SPANSION [ SPANSION ]
