D A T A
S H E E T
TEST CONDITIONS
Table 6.
5.0 V
Test Condition
Device
Under
Test
CL
6.2 kΩ
2.7 kΩ
Output Load
Output Load Capacitance, C
L
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement
reference levels
Note:
Diodes are IN3064 or equivalent
Output timing measurement
reference levels
30
5
0.0–3.0
1.5
1.5
-45
All others Unit
1 TTL gate
100
20
0.45–2.4
0.8
2.0
pF
ns
V
V
V
Test Specifications
Figure 7.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
OUTPUTS
20
Am29F010B
Am29F010B_00_C7 October 31, 2006