DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with
DQ6, indicates whether a particular sector is
actively erasing (that is, the Embedded Erase
algorithm is in progress), or whether that sec-
tor is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at ad-
dresses within those sectors that were selected
for erasure. (The system may use either OE#
or CE# to control the read cycles.) But DQ2
cannot distinguish whether the sector is ac-
tively erasing or is erase-suspended. DQ6, by
comparison, indicates whether the device is ac-
tively erasing, or is in Erase Suspend, but can-
not distinguish which sectors are selected for
erasure. Thus, both status bits are required for
sector and mode information. Refer to
Table 15,
on page 33
to compare outputs for DQ2 and
DQ6.
Figure 7, on page 31
shows the toggle bit algo-
rithm in flowchart form, and the section
“DQ2:
Toggle Bit II” on page 32
explains the algo-
rithm. See also the DQ6: Toggle Bit I subsec-
tion.
Figure 21, on page 45
timing diagram.
shows
the differences b etween DQ2 and DQ 6 in
graphical form.
write the reset command to return to reading
array data.
The remaining scenario is that the system ini-
tially determines that the toggle bit is toggling
and DQ5 has not gone high. The system may
continue to monitor the toggle bit and DQ5
through successive read cycles, determining
the status as described in the previous para-
graph. Alternatively, it may choose to perform
other system tasks. In this case, the system
must start at the beginning of the algorithm
when it returns to determine the status of the
operation (top of
Figure 7, on page 31).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase
time exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle
was not successfully completed.
The device may output a “1” on DQ5 if the sys-
tem tries to program a “1” to a location that
was previously programmed to “0.”
Only an
erase operation can change a “0” back to a
“1.”
Under this condition, the device halts the
operation, and when the timing limit is ex-
ceeded, DQ5 produces a “1.”
Under both these conditions, the system must
write the reset command to return to the read
mode (or to the erase-suspend-read mode if
the device was previously in the erase-sus-
pend-program mode).
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 7, on page 31
for the following
discussion. Whenever the system initially be-
gins reading toggle bit status, it must read
DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the
system would note and store the value of the
toggle bit after the first read. After the second
read, the system would compare the new value
of the toggle bit with the first. If the toggle bit
is not toggling, the device completed the pro-
gram or erase operation. The system can read
array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the
system determines that the toggle bit is still
toggling, the system also should note whether
the value of DQ5 is high (see the section on
DQ5). If it is, the system should then deter-
mine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no
longer toggling, the device successfully com-
pleted the program or erase operation. If it is
still toggling, the device did not completed the
operation successfully, and the system must
32
DQ3: Sector Erase Timer
After writing a sector erase command se-
quence, the system may read DQ3 to deter-
mine whether or not erasure started. (The
sector erase timer does not apply to the chip
erase command.) If additional sectors are se-
lected for erasure, the entire time-out also ap-
p l i e s a f t e r e a c h a d d i t i o n a l s e c t o r e ra s e
command. When the time-out period is com-
plete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase com-
mands from the system can be assumed to be
less than 50 µs, the system need not monitor
DQ3. See also the Sector Erase Command Se-
quence section.
After the sector erase command is written, the
system should read the status of DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure that the
device accepted the command sequence, and
then read DQ3. If DQ3 is “1,” the Embedded
Erase algorithm started; all further commands
(except Erase Suspend) are ignored until the
erase operation is complete. If DQ3 is “0,” the
November 15, 2004
Am29LV320D
SPANSION [ SPANSION ]
