Da ta
Shee t
(Prelimi nar y)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Software Protected Mode (SPM):
The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased.
shows the sizes and address
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM):
The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count:
The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
Table 7.1
S25FL032A Protected Area Sizes
Status Register
Block Protect Bits
BP2
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Protected
Address Range
None
3F0000h–3FFFFFh
3E0000h–3FFFFFh
3C0000h–3FFFFFh
380000h–3FFFFFh
300000h–3FFFFFh
200000h–3FFFFFh
000000h–3FFFFFh
Memory Array
Protected
Sectors
(0)
(1) SA63
(2) SA63:SA62
(4) SA63:SA60
(8) SA63:SA56
(16) SA63:SA48
(32) SA63:SA32
(64) SA63:SA0
Unprotected
Address Range
000000h–3FFFFFh
000000h–3EFFFFh
000000h–3DFFFFh
000000h–3BFFFFh
000000h–37FFFFh
000000h–2FFFFFh
000000h–1FFFFFh
None
Unprotected
Sectors
SA63:SA0
SA62:SA0
SA61:SA0
SA59:SA0
SA55:SA0
SA47:SA0
SA31:SA0
None
Protected
Portion of
Total Memory
Area
0
1/64
1/32
1/16
1/8
1/4
1/2
All
7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see
standard
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling
edge of SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Figure 7.1
Hold Mode Operation
SCK
HOLD#
Hold
Condition
(standard
use)
Hold
Condition
(non-standard
use)
September 1, 2006 S25FL032A_00_C0
S25FL032A
11
SPANSION [ SPANSION ]
