Da ta
Shee t
(Prelimi nar y)
Figure 9.9
Page Program (PP) Command Sequence
CS#
Mode
3
0
1
2
3
4
5
6
7
8
9 10
28 29
30 31 32 33 34 35 36 37 38
39
SCK
Mode 0
Command
24-Bit Address
23 22 21
MSB
3
2
1
0
7
6
5
Data Byte 1
4
3
2
1
0
SI
MSB
2072
2074
2075
2073
2076
CS#
40 41 42 43 44 45 46 47 48 49 50
51 52 53 54
55
2077
2078
1
0
SCK
Data Byte 2
Data Byte
3
1
0
7
6
5
4
3
2
1
0
7
MSB
6
Data Byte 256
5
4
3
2
SI
7
MSB
6
5
4
3
2
MSB
9.10
Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see
is a valid address for the SE command. CS# must be
driven low for the entire duration of the SE sequence. The command sequence is shown in
and
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
SE
. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (BP2:BP0) (see
Figure 9.10
Sector Erase (SE) Command Sequence
CS#
Mode
3
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
SCK
Mode 0
Command
24-bit Address
23
MSB
SI
Hi-Z
22
21
3
2
1
0
SO
August 31, 2006 S25FL040A_00_B0
S25FL040A
2079
21
SPANSION [ SPANSION ]
