D a t a
S h e e t
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
Table 1
lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1.
S29AL008D Device Bus Operations
DQ8–DQ15
Addresses
(Note
1)
A
IN
X
X
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
A
IN
DQ0–
DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
D
IN
BYTE#
= V
IH
D
OUT
D
IN
High-Z
High-Z
High-Z
X
BYTE#
= V
IL
DQ8–DQ14 = High-Z,
DQ15 = A-1
High-Z
High-Z
High-Z
X
Operation
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note
2)
CE#
L
L
V
CC
±
0.3 V
L
X
L
OE# WE# RESET#
L
H
X
H
X
H
H
L
X
H
X
L
H
H
V
CC
±
0.3 V
H
L
V
ID
Sector Unprotect (Note
2)
Temporary Sector Unprotect
Legend:
L
X
H
X
L
X
V
ID
V
ID
D
IN
D
IN
X
D
IN
X
High-Z
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V
IH
), A18:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
Sector Protection/Unprotection, on page 16.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in
the byte or word configuration. If the BYTE# pin is set at logic
1,
the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic
0,
the device is in byte configuration, and only data
I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1)
address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
IL
. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at V
IH
. The
BYTE# pin determines whether the device outputs array data in words or bytes.
June 16, 2005 S29AL008D_00A3
S29AL008D
11
SPANSION [ SPANSION ]
