The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V 0.3 V. (Note that this is a more restricted voltage range than
V .) If CE# and RESET# are held at V , but not within V 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
CC
IH
IH
CC
requires standard access time (t ) for read access when the device is in either
CE
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the DC Characteristics table, I
specification.
and I
represents the standby current
CC4
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The
device automatically enables this mode when addresses remain stable for t
+
ACC
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide new data when
addresses are changed. While in sleep mode, output data is latched and always
available to the system. I
in the DC Characteristics table represents the
CC4
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V for at least a period of
IL
t , the device immediately terminates any operation in progress, tristates all
RP
data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V ±0.3 V, the device draws CMOS standby current (I
). If RESET# is held
SS
CC4
at V but not within V ±0.3 V, the standby current will be greater.
IL
SS
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
(during Embedded Algorithms). The system can thus monitor
READY
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of t
(not during Embedded
READY
Algorithms). The system can read data t after the RESET# pin returns to V .
RH
IH
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14
for the timing diagram.
Output Disable Mode
When the OE# input is at V , output from the device is disabled. The output pins
IH
are placed in the high impedance state.
13
S29AL016M
S29AL016M_00A4 April 21, 2004
SPANSION [ SPANSION ]
