D a t a
S h e e t
Test Conditions
3.3 V
Table 13.
Test Specifications
90, 100
Unit
Test Condition
Output Load
Output Load Capacitance, C
L
(including jig capacitance)
Device
Under
Test
CL
6.2 kΩ
2.7 kΩ
1 TTL gate
30
5
0.0 or V
CC
0.5 V
CC
0.5 V
CC
pF
ns
V
V
V
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
Note:
Diodes are IN3064 or equivalent
Figure 11.
Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
OUTPUTS
V
CC
0.0 V
Input
0.5 V
CC
Measurement Level
0.5 V
CC
Output
Figure 12. Input Waveforms and Measurement Levels
42
S29AL016M
S29AL016M_00_A7 October 11, 2006