A d v a n c e
I n f o r m a t i o n
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
See
Table 1 on page 11
for description of bus operations.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.
No unlock or command cycles required when reading array data.
The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device
is providing status data).
The fourth cycle of the autoselect command sequence is a read cycle.
For Model 03, the data is 8Dh for factory locked and 0Dh for not factory locked. For Model 04, the data is 9Dh for factory locked and 1Dh
for not factory locked.
10. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also
acceptable.
14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation.
15. The Erase Resume command is valid only during the Erase Suspend mode.
Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5,
DQ6, DQ7, and RY/BY#.
Table 18 on page 44
and the following subsections describe the functions
of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or
erase operation is complete or in progress. These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in
progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the
rising edge of the final WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-
mately 1 µs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling produces a
0
on DQ7. When the Embedded
Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling pro-
duces a
1
on DQ7. This is analogous to the complement/true datum output described for the
Embedded Program algorithm: the erase function changes all the bits in a sector to
1;
prior to
this, the device outputs the
complement,
or
0.
The system must provide an address within any
of the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data, it can read valid
data at DQ7–DQ0 on the
following
read cycles. This is because DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted low.
Figure 21, on page 57,
Data# Polling
Timings (During Embedded Algorithms), in the
AC Characteristics on page 50
June 13, 2005 S29AL032D_00_A3
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