Data
She et
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device.
lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Table 8.1
Device Bus Operations
DQ8–DQ15
Operation
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
V
ID
= 11.5–12.5 V
V
HH
= 11.5–12.5 V
X = Don’t Care
SA = Sector Address
A
IN
= Address In
D
IN
= Data In
D
OUT
= Data Out
Notes
1. If WP# = V
IL
, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot sector devices). If WP#
= VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method described in Write Protect (WP#). All
sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
2. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see
CE#
L
L
L
V
CC
±
0.3V
L
X
OE#
L
H
H
X
H
X
WE#
H
L
L
X
H
X
RESET#
H
H
H
V
CC
±
0.3V
H
L
WP#
X
X
X
X
ACC
X
X
V
HH
H
X
X
Addresses
A
IN
A
IN
A
IN
X
X
X
DQ0–
DQ7
D
OUT
High-Z
High-Z
High-Z
BYTE#
= V
IH
D
OUT
High-Z
High-Z
High-Z
BYTE#
= V
IL
DQ8–DQ14
= High-Z,
DQ15 = A-1
High-Z
High-Z
High-Z
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic
1,
the device is in word configuration, DQ0–DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic
0,
the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
IH
.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See
for more information. Refer to the AC Read-Only Operations table for
timing specifications and the timing diagram. Refer to the DC Characteristics table for the active current
specification on reading array data.
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit
®
Flash Family
17
SPANSION [ SPANSION ]
