D at a
S hee t
Table 15.2
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
t
Ready
t
Ready
t
RP
t
RH
t
RPD
t
RB
Note
Not 100% tested.
Description
RESET# Pin Low (During Embedded Algorithms) to Read Mode
RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode
RESET# Pulse Width
Reset High Time Before Read
RESET# Input Low to Standby Mode
RY/BY# Output High to CE#, OE# pin Low
Max
Max
Min
Min
Min
Min
All Speed Options
20
500
500
50
20
0
Unit
μs
ns
ns
ns
µs
ns
Figure 15.4
Reset Timings
RY/BY#
CE#, OE#
t
RH
RESET#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
t
RH
RESET#
t
RP
Notes
1. Not 100% tested.
2. See the
for more information.
3. For 1–16 words/1–32 bytes programmed.
66
S29GL-N MirrorBit
®
Flash Family
S29GL-N_01_09 November 16, 2007