D a t a S h e e t
AC Characteristics
Erase and Program Operations
Parameter
Speed Options
90
(Note 6)
JEDEC
Std.
Description
Write Cycle Time (Note 1)
100
100
110
110
Unit
t
t
Min
Min
90
110
110
ns
ns
AVAV
WC
t
t
t
Address Setup Time
0
15
45
0
AVWL
AS
Address Setup Time to OE# low during toggle bit
polling
t
Min
Min
Min
ns
ns
ns
ASO
t
Address Hold Time
WLAX
AH
Address Hold Time From CE# or OE# high
during toggle bit polling
t
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
45
0
ns
ns
DVWH
WHDX
DS
t
Data Hold Time
DH
t
CE# High during toggle bit polling
Output Enable High during toggle bit polling
20
20
CEPH
OEPH
t
ns
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
ELWL
WHEH
WLWH
CS
CH
WP
t
t
CE# Hold Time
t
t
Write Pulse Width
35
30
240
t
t
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
WHDL
WPH
Effective Write Buffer Program
Per Word
Typ
15
µs
Operation (Notes 2, 4)
Accelerated Effective Write Buffer
Per Word
t
t
t
t
Typ
Typ
Typ
13.5
60
µs
µs
µs
WHWH1
WHWH2
WHWH1
WHWH2
Program Operation (Notes 2, 4)
Program Operation (Note 2)
Word
Word
Accelerated Programming Operation
(Note 2)
54
Sector Erase Operation (Note 2)
Typ
Min
Min
Max
0.5
250
50
sec
ns
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
µs
VCS
t
Erase/Program Valid to RY/BY# Delay
90
ns
BUSY
Notes:
1. Not 100% tested.
2. See the Erase And Programming Performance‚ on page 87 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with V = V = 3 V. AC specifications
IO
CC
for 110 ns speed options are tested with V = 1.8 V and V = 3.0 V.
IO
CC
6. 90 ns speed option only applicable to S29GL128N and S29GL256N.
80
S29GL-N MirrorBit™ Flash Family
S29GL-N_00_B3 October 13, 2006
SPANSION [ SPANSION ]
