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S29WS512P0PBFW003 参数 Datasheet PDF下载

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型号: S29WS512P0PBFW003
PDF下载: 下载PDF文件 查看货源
内容描述: MirrorBit㈢闪存系列512/256/128 MB( 32/16/8的M× 16位), 1.8 V突发同时读/写的MirrorBit闪存 [MirrorBit㈢ Flash Family 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory]
分类和应用: 闪存
文件页数/大小: 94 页 / 3304 K
品牌: SPANSION [ SPANSION ]
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Data
She et
7.1
Device Operation Table
The device must be setup appropriately for each operation.
describes the required state of each
control pin for any particular operation.
Table 7.1
Device Operations
Operation
Asynchronous Read
- Addresses Latched
Asynchronous Read
AVD# Steady State
Asynchronous Write
Synchronous Write
Standby (CE#)
Hardware Reset
Burst Read Operations
Latch Starting Burst Address by CLK
Advance Burst read to next address
Terminate current Burst read cycle
Terminate current Burst read cycle
via RESET#
Terminate current Burst read cycle
and start new Burst read cycle
L
L
H
X
L
X
L
X
X
X
H
H
H
H
H
X
X
L
H
X
X
Addr In
X
X
X
Addr In
Output
Invalid
Output
Valid
HIGH Z
HIGH Z
Output
Invalid
= toggle.
X
H
HIGH Z
HIGH Z
X
H
H
H
L
H
CE#
L
L
L
L
H
X
OE#
L
L
H
H
X
X
L
X
X
X
X
X
X
WE#
H
H
CLK
X
X
X
L
L
AVD#
Amax–A0
Addr In
Addr In
Addr In
Addr In
X
X
DQ15–0
Output
Valid
Output
Valid
Input
Valid
I/O
HIGH Z
HIGH Z
RDY
H
H
H
H
HIGH Z
HIGH Z
RESET#
H
H
H
H
H
Legend:
L = Logic 0, H = Logic 1, X = can be either V
IL
or V
IH
.,
Note:
Address is latched on the rising edge of clock.
= rising edge,
= high to low,
7.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from
one memory location at a time. Addresses are presented to the device in random order, and the propagation
delay through the device causes the data on its outputs to arrive asynchronously with the address on its
inputs.
The device defaults to reading array data asynchronously after device power-up or hardware reset. To read
data from the memory array, the system must first assert a valid address on A
max
–A0, while driving AVD#
and CE# to V
IL
. WE# must remain at V
IH
. The rising edge of AVD# latches the address, preventing changes
to the address lines from effecting the address being accessed.. Data is output on DQ15-DQ0 pins after the
access time (t
ACC
) has elapsed from the falling edge of AVD#, or the last time the address lines changed
while AVD# was low.
September 28, 2007 S29WS-P_00_A11
S29WS-P
19