Da t a
Sh ee t
5.4
S71PL129N—TLA064
Figure 5.5
64-ball Fine-Pitch Ball Grid Array (S71PL129N)
A1
DNU
B5
RFU
C3
A7
D2
A3
E2
A2
F2
A1
G2
A0
H2
F-CE1#
J2
R-CE1#
D3
A6
E3
A5
F3
A4
G3
VSS
H3
OE#
J3
DQ0
K3
DQ8
C4
R-LB#
D4
R-UB#
E4
A18
F4
A17
G4
DQ1
H4
DQ9
J4
DQ10
K4
DQ2
H5
DQ3
J5
F-VCC
K5
DQ11
L5
RFU
M1
DNU
H6
DQ4
J6
R-VCC
K6
RFU
L6
RFU
C5
F-WP#/
ACC
A10
DNU
B6
RFU
C6
WE#
D6
R-CE2
E6
A20
C7
A8
D7
A19
E7
A9
F7
A10
G7
DQ6
H7
DQ13
J7
DQ12
K7
DQ5
C8
A11
D8
A12
E8
A13
F8
A14
G8
RFU
H8
DQ15
J8
DQ7
K8
DQ14
D9
A15
E9
A21
F9
F-CE2#
pSRAM Only
G9
A16
H9
RFU
J9
VSS
Do Not Use/
Reserved for Future Use
Flash Only
Shared
Legend
D5
F-RST
E5
F-RY/BY#
M10
DNU
Note:
Top view—balls facing down.
The addresses that are shared vary by MCP combination as shown in the table below:
Flash-only Addresses
S71PL129NB0
S71PL129NC0
A21
—
Shared Addresses
A20:A0
A21:A0
December 8, 2006 S71PL-N_00_A9
S71PL-N MirrorBit
TM
MCPs
9
SPANSION [ SPANSION ]
