A d v a n c e
I n f o r m a t i o n
Input/Output Description
Pin Description
A21–A0
DQ15–DQ0
CE1#f
CE2#f
CE1#ps
CE2ps
OE#
WE#
RY/BY#
UB#
LB#
RESET#
WP#/ACC
V
CC
f
=
=
=
=
=
=
=
=
=
=
=
=
=
=
22 Address Inputs (Common)
16 Data Inputs/Outputs (Common)
Chip Enable 1 (Flash)
Chip Enable 2 (Flash)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low (Flash 1)
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
V
CC
ps
V
SS
NC
=
=
=
Logic Symbol
22
A21–A0
16
CE1#f
CE2#f
CE1#ps
CE2ps
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
RY/BY#
DQ15–DQ0
8
S71PL129Jxx_00_A5 December 23, 2004
SPANSION [ SPANSION ]
