CY28158
Function Table
[2]
SEL133/
100#
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SEL1
0
1
0
1
0
1
0
1
SEL0
Hi-Z
100.227
[3]
100
100
TCLK/2
N/A
133.33
133.33
CPU
(MHz)
Hi-Z
66.818
[3]
66.67
66.67
TCLK/4
N/A
66.67
66.67
3V66
(MHz)
Hi-Z
33.409
[3]
33.33
33.33
TCLK/8
N/A
33.33
33.33
PCI
(MHz)
48MHZ
(MHz)
Hi-Z
48.008
[3]
OFF
48.008
[3]
TCLK/2
N/A
OFF
48.008
[3]
Hi-Z
14.318
[3]
14.318
14.318
TCLK
N/A
14.318
14.318
REF
(MHz)
IOAPIC
(MHz)
Hi-Z
16.705
[3]
16.67
16.67
TCLK/16
N/A
16.67
16.67
Actual Clock Frequency Values
Clock Output
CPU
CPU
48MHZ
Target
Frequency
(MHz)
100.0
133.33
48.0
Actual
Frequency
(MHz)
99.126
132.769
48.008
PPM
–8740
–4208
167
Clock Enable Configuration
CPU_STOP#
X
0
0
1
1
PWR_DWN#
0
1
1
1
1
PCI_STOP#
X
0
1
0
1
CPU
LOW
LOW
LOW
ON
ON
3V66
LOW
LOW
LOW
ON
ON
PCI
LOW
LOW
ON
LOW
ON
PCI_F
LOW
ON
ON
ON
ON
REF
IOAPIC
LOW
ON
ON
ON
ON
OSC.
OFF
ON
ON
ON
ON
VCOs
OFF
ON
ON
ON
ON
Clock Driver Impedances
Impedance
Minimum
Buffer Name
CPU, IOAPIC
48MHZ, REF
PCI, 3V66
V
DD
Range
2.375V – 2.625V
3.135V – 3.465V
3.135V – 3.465V
Buffer Type
Type 1
Type 3
Type 5
13.5
20
12
29
40
30
45
60
55
Typical
Maximum
Note:
2. TCLK is a test clock driven in on the X1 input in test mode.
3. This selection is defined as “N/A” or “Reserved.”
Rev 1.0, November 20, 2006
Page 3 of 9
SPECTRALINEAR [ SPECTRALINEAR INC ]
