CY28326
Byte 10: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name/Pin Affected
CPU_FSEL_N8
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
Description
Dial-A-Frequency Enable bit is set, the values programmed in
CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the
CPU output frequency.
This setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the latched FS[D:A] register will be used. When it is set, the
frequency ratio stated in the SEL[3:0] register will be used.
Byte 11: Control Register
Bit
7
6
@Pup
0
0
Name/Pin Affected
Dial_A_Frequency
Enable
Description
Dial-A-Frequency output frequencies enabled
0 = Disabled, 1 = Enabled
WD Timer Reload & Reset To enable this function the register bit must first be set to “0”
before toggling to “1”
0 = Do not reload, 1 =Reset timer but continue to count.
Test bit
Test bit
Test bit
Test bit
24-48 M_SEL
Don’t change, Default =1
Don’t change, Default =0
Don’t change, Default =0
Don’t change, Default =0
“0” = 48 MHz, “1” = 24 MHz, default = “0”, level can be change during BIOS
boot up only. System will hang if this configuration is changed after system
boots.
Don’t change, Default =1
5
4
3
2
1
1
0
0
0
HW
0
1
Test bit
Rev 1.0, November 20, 2006
Page 9 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
