CY28326
Table 5. Block Read and Block Write protocol
(continued)
46
....
....
....
....
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
38
46:39
47
55:48
56
....
....
....
...
Table 6. Byte Read and Byte Write protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Byte Configuration Map
Byte 0: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
HW
HW
HW
HW
0
1
1
1
Name/Pin Affected
FSD
FSC
FSB
FSA
Test bit
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Don’t change, Default =0
CPU[T/C]2 Output Enable
0 = Disabled (tri-sate), 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disabled (tri-sate), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disabled (tri-sate), 1 = Enabled
Description
HW Frequency selection bits [3:0]. See table 2.
Power up latched value
Rev 1.0, November 20, 2006
Page 5 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
