CY28329
Data Byte 1:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Byte 2:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Byte 3:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
38
39
7
6
5
7
6
5
Name
DOT
USB
PCI_F2
PCI_F1
PCI_F0
PCI_F2
PCI_F1
PCI_F0
Pin Description
DOT 48 MHz Output Enable, 1 = enabled, 0 = disabled
USB 48 MHz Output Enable, 1 = enabled, 0 = disabled
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
PCI_F2 Output Enable, 1 = enabled, 0 = disabled
PCI_F1Output Enable, 1 = enabled, 0 = disabled
PCI_F0 Output Enable, 1 = enabled, 0 = disabled
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power On
Default
1
1
0
0
0
1
1
1
Pin#
–
18
17
16
13
12
11
10
Name
–
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Reserved, set = 0
PCI6 Output Enable
1 = Enabled; 0 = Disabled
PCI5 Output Enable
1 = Enabled; 0 = Disabled
PCI4 Output Enable
1 = Enabled; 0 = Disabled
PCI3 Output Enable
1 = Enabled; 0 = Disabled
PCI2 Output Enable
1 = Enabled; 0 = Disabled
PCI1 Output Enable
1 = Enabled; 0 = Disabled
PCI0 Output Enable
1 = Enabled; 0 = Disabled
Pin Description
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power On
Default
0
1
1
1
1
1
1
1
Pin#
–
53, 54
–
–
–
44, 45
48, 49
51, 52
CPU3
CPU3#
–
–
–
CPU2
CPU2#
CPU1
CPU1#
CPU0
CPU0#
Name
CPU Mult0 Value
CPU3 Output Enable
1 = Enabled; 0 = Disabled
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
CPU2 Output Enable
1 = Enabled; 0 = Disabled
CPU1Output Enable
1 = Enabled; 0= Disabled
CPU0 Output Enable
1 = Enabled; 0 = Disabled
Description
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power On
Default
HW
1
0
0
0
1
1
1
Rev 1.0, November 24, 2006
Page 5 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
