CY28354-400
Absolute Maximum Conditions[1]
Parameter
Description
Supply Voltage to Ground Potential
Min.
–0.5
–0.3
1.1
Max.
4.6
Unit
V
VDD
Vin
DC Input Voltage (except BUFF_IN)
Output Voltage
VDD+0.3
VDD–0.4
+150
V
Vout
Ts
V
Temperature, Storage
–65
0
°C
Ta
Temperature, Operating Ambient
85
°C
ØJC
ØJA
ESDh
Dissipation, Junction to Case (Mil-Spec 883E Method 1012.1)
Dissipation, Junction to Ambient (JEDEC (JESD 51)
ESD Protection (Human Body Model)
36.39
77.99
°C/W
°C/W
V
–
2000
DC Electrical Specifications
Parameter
Description
Min.
2.3
–
Typ.
Max.
2.7
–
Unit
V
VDD2.5
COUT
CIN
Supply Voltage
–
6
5
Output Capacitance
Input Capacitance
pF
pF
–
–
AC Electrical Specifications
Parameter
VIL
Description
Input LOW Voltage
Input HIGH Voltage
Output HIGH Current
Output LOW Current
Output LOW Voltage[2]
Output HIGH Voltage[2]
Supply Current[2]
Conditions
Min.
Typ.
Max.
Unit
V
For all pins except SMBus
0.3
–
0.7
VIH
1.7
–
VDD + 0.3
V
IOH
VDD = 2.375V, VOUT = 1V
VDD = 2.375V, VOUT = 1.2V
IOL = 12 mA, VDD = 2.375V
IOH = –12 mA, VDD = 2.375V
Unloaded outputs, 133 MHz
Loaded outputs, 133 MHz
All outputs off
–
–
–12
mA
mA
V
IOL
–
–
12
VOL
VOH
IDD
–
–
0.5
1.7
–
–
400
V
–
–
mA
mA
mA
V
IDD
Supply Current
–
–
500
IDDPD
VOUT
VOC
INDC
Supply Current
–
0.7
–
–
2
Output Voltage Swing
Output Crossing Voltage
Input Clock Duty Cycle
See Test Circuity. See Figure 1
VDD + 0.6
VDD/2+0.3
60
VDD/2–0.3
40
VDD/2
–
V
%
Switching Characteristics[3]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
210
Unit
MHz
%
–
Operating Frequency
Duty Cycle[2, 4] = t2 yꢀt1
DDR Rising Edge Rate[2] Measured single ended at 20% to 80% of VDIF
DDR Falling Edge Rate[2] Measured single ended at 80% to 20% of VDIF
Output to Output Skew for All outputs equally loaded.
60
INDC –2%
1.0
–
Measured differentially at VCROSS
–
INDC +2%
5.0
t3d
t4d
t5
2.0
2.0
–
V/ns
V/ns
ps
1.0
5.0
–
75
DDR[2]
See Figure 1.
t6
InputtoOutputPropagation At output load of 15 pFn
delay
–
–
6
ns
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3. All parameters specified with loaded outputs.
4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Rev 1.0,November 22, 2006
Page 5 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
