CY28404
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Byte 0: Control Register 0
Bit
7
6
0
1
@Pup
Reserved
PCIF
PCI
Reserved
FS_E
FS_D
FS_C
FS_B
FS_A
Name
Reserved, set = 0
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
Reserved, set = 0
Power up latched value of FS_E pin
Power up latched value of FS_D pin
Power up latched value of FS_C pin
Power up latched value of FS_B pin
Power up latched value of FS_A pin
Description
5
4
3
2
1
0
0
HW
HW
HW
HW
HW
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
@Pup
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPUT1, CPUC1
CPUT0, CPUC0
Name
Reserved, set = 0
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
CPU(T/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Description
Rev 1.0, November 22, 2006
Page 5 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
