CY28404
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
@Pup
Reserved
Reserved
Reserved
CPUT1, CPUC1
CPUT0, CPUC0
Reserved
Reserved
Reserved
Name
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state
CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
Description
Byte 3: Control Register 3
Bit
7
1
@Pup
Name
SW PCI STOP
Description
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP de-assert
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume
in a synchronous manner with no short pulses.
Reserved, set = 1
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Reserved
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Byte 4: Control Register 4
Bit
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
1
@Pup
Name
USB_48 and 24_48MHz
USB_48
PCIF2
PCIF1
PCIF0
PCIF2
PCIF1
PCIF0
Description
USB_48 and 24_48MHz Drive Strength Control
0 = High Drive Strength, 1 = Low Drive Strength
USB_48 Output Enable
0 = Disabled, 1 = Enabled
Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Rev 1.0, November 22, 2006
Page 6 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
