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CY28410ZC 参数 Datasheet PDF下载

CY28410ZC图片预览
型号: CY28410ZC
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为英特尔的Grantsdale芯片组 [Clock Generator for Intel Grantsdale Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 17 页 / 220 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28410  
Figure 1. Crystal Capacitive Clarification  
Calculating Load Capacitors  
In addition to the standard external trim capacitors, trace  
capacitance and pin capacitance must also be considered to  
correctly calculate crystal loading. As mentioned previously,  
the capacitance on each side of the crystal is in series with the  
crystal. This means the total capacitance on each side of the  
crystal must be twice the specified crystal load capacitance  
(CL). While the capacitance on each side of the crystal is in  
series with the crystal, trim capacitors (Ce1,Ce2) should be  
calculated to provide equal capacitive loading on both sides.  
Clock Chip  
Ci2  
Ci1  
Pin  
3 to 6p  
X2  
X1  
Cs2  
Cs1  
Trace  
2.8pF  
XTAL  
Ce1  
Ce2  
Trim  
33pF  
Figure 2. Crystal Loading Example  
As mentioned previously, the capacitance on each side of the  
crystal is in series with the crystal. This mean the total capac-  
itance on each side of the crystal must be twice the specified  
load capacitance (CL). While the capacitance on each side of  
the crystal is in series with the crystal, trim capac-  
itors(Ce1,Ce2) should be calculated to provide equal capaci-  
tance loading on both sides.  
Load Capacitance (each side)  
Ce = 2 * CL – (Cs + Ci)  
Total Capacitance (as seen by the crystal)  
1
CLe  
=
Use the following formulas to calculate the trim capacitor  
values fro Ce1 and Ce2.  
1
Ce2 + Cs2 + Ci2  
1
Ce1 + Cs1 + Ci1  
(
)
+
CL ................................................... Crystal load capacitance  
(lead frame, bond wires etc.)  
CLe .........................................Actual loading seen by crystal  
using standard value trim capacitors  
PD (Power-down) Clarification  
The VTT_PWRGD# /PD pin is a dual function pin. During initial  
power-up, the pin functions as VTT_PWRGD#. Once  
VTT_PWRGD# has been sampled low by the clock chip, the  
pin assumes PD functionality. The PD pin is an asynchronous  
active high input used to shut off all clocks cleanly prior to  
Ce .....................................................External trim capacitors  
Cs ............................................. Stray capacitance (terraced)  
Ci .......................................................... Internal capacitance  
Rev 1.0,November 21, 2006  
Page 8 of 17