CY2SSTV16859
Pin Configuration
(continued)
VDDQ
VDDQ
VDDQ
Q10A
Q11A
Q12A
Q13A
GND
VDD
Q8A
Q9A
D13
D12
D11
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
1
2
3
4
5
6
7
8
9
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
31
30
D10
D9
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
D5
D4
10
11
12
13
14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29
VDD
VDDQ
VDDQ
VDDQ
Q7B
Q6B
Q5B
Q4B
Q3B
Q2B
Q1B
D1
D2
56 QFN Package
Pin Description
Pin
TSSOP
51
7,15,34,39,43,50,54,58,63
37,46,60
6,18,27,33,38,47,59,64
45
16,14,13,12,11,10,9,8,5,4,3,2,1
38
37,48
26,33,45
9,17,23,27,34,44,49,55
32
7,6,5,4,3,2,1,56,54,53,52,51,50
QFN
RESET#
GND
VDD
VDDQ
VREF
QA(1:13)
QB(1:13)
D(1:13)
Disable Clocking and Reset Latch
Ground
Supply Voltage
Supply Voltage, Quiet
Reference Voltage for Data Inputs
D(1:13)
Data Outputs
Data Outputs
Data Inputs
Name
Description
32,31,30,29,28,25,24,23,22,21,20, 22,21,20,19,18,16,15,14,13,12
19,17
11,10,8
35,36,40,41,42,44,52,53,55,56,57, 24,25,28,29,30,31,39,40,41,42
61,62
43,46,47
48,49
Table 1. Function Table
[1,2,3]
INPUTS
RESET#
H
H
H
L
Notes:
1. H = High voltage level.
2. L = Low voltage level.
3. X = Don’t care.
35,36
CLK, CLK#
Differential Clock Signals
D3
OUTPUT
CLK#
D
L
H
Q
L
H
Q
0
L
CLK
L or H
X or floating
L or H
X or floating
X
X or floating
Rev 1.0, November 21, 2006
Page 2 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
