CY2SSTV8575
Pin Description
Pin
5,6
21
22
2,12,15,27,30
1,11,16,28,31
18
Name
CLK, CLK#
FBIN#
FBIN
Y(0:4)
Y(0:4)#
FBOUT
I/O
I
I
I
O
O
O
Differential Outputs
Differential Outputs
Type
LV Differential Input
Differential Input
Description
Differential Clock Input
Feedback Clock Input.
Connect to FBOUT# for accessing the
PLL.
Feedback Clock Input.
Connect to FBOUT for accessing the
PLL.
Clock + Outputs
Clock – Outputs
Feedback Clock Output.
Connect to FBIN for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
Feedback Clock Output.
Connect to FBIN# for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
Output Enable Input.
When OE is set HIGH, all Q and Q#
outputs are enabled and switch at the same frequency as CLK.
When set LOW, all Q and Q# outputs are disabled (Hi-Z) and
the PLL is powered down.
2.5V Nominal
2.5V Nominal
2.5V Power Supply for Output Clock Buffers
2.5V Power Supply for PLL.
When AVDD is at GND, PLL is
bypassed and CLK is buffered directly to the device outputs.
During disable (OE = 0), the PLL is powered down.
Common Ground
Analog Ground
19
FBOUT#
O
23
OE
I
3,4,7,13,20,26,
29
8
VDDQ
AVDD
10,14,17,24,25,
32
9
VSS
AVSS
0.0V Ground
0.0V Analog Ground
Table 1. Function Table
INPUTS
AVDD
GND
GND
X
X
2.5V
2.5V
2.5V
OE
H
H
L
L
H
H
H
CLK
L
H
L
H
L
H
< 20 MHz
CLK#
H
L
H
L
H
L
< 20 MHz
Y
L
H
Z
Z
L
H
Hi-Z
Y#
H
L
Z
Z
H
L
Hi-Z
OUTPUTS
FBOUT
L
H
Z
Z
L
H
Hi-Z
FBOUT#
H
L
Z
Z
H
L
HI-Z
BYPASSED/OFF
BYPASSED/OFF
Off
OFF
On
On
Off
PLL
Rev 1.0, November 25, 2006
Page Page 2 of
SPECTRALINEAR [ SPECTRALINEAR INC ]
