SL15101
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS
FIN=30MHz and all 4 clocks are
at 66MHz and +/-2.0% Spread
and CL=0
PD#=GND
Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK
Minimum setting value
PCin
PCout
Maximum setting value
Resolution (programming steps)
CIN2
Pins 4 and 8
If programmed as PD#, OE,
SSON or FS
Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK
Input High Current
IIH
-15
-
15
A
Input Low Current
IIL
-15
-
15
A
Pull-up or Down Resistors
RPU/D
100
160
220
k
Operating Supply Current
Standby Current
Output Leakage Current
Programmable
Input Capacitance at
Pins 2 and 3
IDD
ISBC
IOL
-
-
-10
-
-
-
-
8.2
80
-
8
40
0.5
4
9.8
100
10
-
-
-
6
mA
A
A
pF
pF
pF
pF
Input Capacitance
Load Capacitance
CL
-
-
15
pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter
Input Frequency Range
Input Frequency Range
Symbol
FIN1
FIN2
Condition
Crystal or Ceramic Resonator
External Clock
SSCLK
REFCLK, crystal or resonator input
REFCLK, clock input
SSCLK
REFCLK, Xtal input
REFCLK, clock input
Clock Input, Pin 3
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Min
8
8
3
0.25
0.25
45
45
40
40
-
Typ
-
-
-
-
-
50
50
50
50
4.00
Max
48
166
200
48
166
55
55
60
60
4.80
Unit
MHz
MHz
MHz
MHz
MHz
%
%
%
%
ns
Output Frequency Range
FOUT1
Output Frequency Range
FOUT2
Output Frequency Range
FOUT3
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Input Duty Cycle
Output Rise/Fall Time
DC1
DC2
DC3
DCIN
tr/f1
Rev 1.8, August 10, 2007
Page 9 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
