2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Data Sheet
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz
is initiated by executing an 8-bit command, 0BH, followed
by address bits [A
23
-A
0
] and a dummy byte. CE# must
remain active low for the duration of the High-Speed-Read
cycle. See Figure 5 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
4 Mbit density, once the data from address location
07FFFFH has been read, the next output will be from
address location 000000H.
CE#
MODE 3
SCK
MODE 0
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SI
MSB
SO
0B
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
X
N
D
OUT
MSB
N+1
D
OUT
N+2
D
OUT
N+3
D
OUT
1242 F05.0
N+4
D
OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)
FIGURE 5: H
IGH
-S
PEED
-R
EAD
S
EQUENCE
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
10
SST [ SILICON STORAGE TECHNOLOGY, INC ]
