2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Data Sheet
PRODUCT IDENTIFICATION
TABLE 2: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST25LF020A
SST25LF040A
00001H
00001H
43H
44H
T2.0 1242
DEVICE OPERATION
The SST25LF020A/040A is accessed through the SPI
(Serial Peripheral Interface) bus compatible protocol. The
SPI bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through the
Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK).
The SST25LF020A/040A supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state
of the SCK signal when the bus master is in Stand-by
mode and no data is being transferred. The SCK signal is
low for Mode 0 and SCK signal is high for Mode 3. For both
modes, the Serial Data In (SI) is sampled at the rising edge
of the SCK clock signal and the Serial Data Output (SO) is
driven after the falling edge of the SCK clock signal.
Data
BFH
00000H
MEMORY ORGANIZATION
The SST25LF020A/040A SuperFlash memory array is
organized in 4 KByte sectors with 32 KByte overlay blocks.
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1242 F02.0
HIGH IMPEDANCE
FIGURE 2: SPI P
ROTOCOL
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
