2 Mbit / 4 Mbit SPI Serial Flash
SST25VF040
EOL Product Data Sheet
Read
The Read instruction outputs the data starting from the
specified address location. The data output stream is con-
tinuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
4 Mbit density, once the data from address location
7FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A
23
-A
0
]. CE# must
remain active low for the duration of the Read cycle. See
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI
MSB
SO
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
N
D
OUT
MSB
1231 F04.1
N+1
D
OUT
N+2
D
OUT
N+3
D
OUT
N+4
D
OUT
FIGURE 5: R
EAD
S
EQUENCE
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A
23
-A
0
]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait T
BP
for the completion of the internal
self-timed Byte-Program operation. See Figure 6 for the
Byte-Program sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39
SCK
MODE 0
SI
MSB
02
ADD.
MSB
ADD.
ADD.
D
IN
MSB
LSB
SO
HIGH IMPEDANCE
1231 F05.1
FIGURE 6: Byte-Program Sequence
©2006 Silicon Storage Technology, Inc.
S71231(04)-00-000
10/06
9
SST [ SILICON STORAGE TECHNOLOGY, INC ]
