512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
by executing an 8-bit command, 60H. CE# must be driven
high before the instruction is executed. The user may poll
the Busy bit in the software status register or wait T
CE
for
the completion of the internal self-timed Chip-Erase cycle.
See Figure 9 for the Chip-Erase sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
MODE 0
SI
MSB
60
HIGH IMPEDANCE
1192 F07.12
SO
FIGURE 9: C
HIP
-E
RASE
S
EQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 10 for the RDSR instruction sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
SO
MODE 0
05
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1192 F37.7
FIGURE 10: R
EAD
-S
TATUS
-R
EGISTER
(RDSR) S
EQUENCE
©2004 Silicon Storage Technology, Inc.
S71192-06-000
4/04
11
SST [ SILICON STORAGE TECHNOLOGY, INC ]
