512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
MODE 0
SI
MSB
06
HIGH IMPEDANCE
1192 F35.6
SO
FIGURE 11: W
RITE
E
NABLE
(WREN) S
EQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
MODE 0
SI
MSB
04
HIGH IMPEDANCE
1192 F36.6
SO
FIGURE 12: W
RITE
D
ISABLE
(WRDI) S
EQUENCE
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-Write-
Status-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write-
©2004 Silicon Storage Technology, Inc.
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
S71192-06-000
4/04
12
SST [ SILICON STORAGE TECHNOLOGY, INC ]
