16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Read Operation
The Read operation is controlled by CE# and OE#; both
have to be low for the system to obtain data from the out-
puts. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in a high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 7).
To meet high-density, surface-mount requirements, these
devices are offered in 48-ball TFBGA and 48-lead TSOP
packages. See Figures 5 and 6 for pin assignments.
Program Operation
Device Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
The Program operation is accomplished in three steps:
1. Software Data Protection is initiated using the
three-byte load sequence.
Auto Low Power Mode
2. Address and data are loaded.
These devices also have the Auto Lower Power mode
which puts them in a near standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the IDD active Read current to 4 µA typically.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
Concurrent Read/Write Operation
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank.
See Figures 8 and 9 for WE# and CE# controlled Program
operation timing diagrams and Figure 23 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.
CONCURRENT READ/WRITE STATE
Bank 1
Read
Bank 2
No Operation
Write
Read
Write
Read
Write
No Operation
Read
No Operation
No Operation
Write
Note: For the purposes of this table, write means to perform Block-
or Sector-Erase or Program operations as applicable to the
appropriate bank.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
2
SST [ SILICON STORAGE TECHNOLOGY, INC ]
