1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
TABLE 2: P
IN
D
ESCRIPTION
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
Pin Name
Address Inputs
Data Input/output
Functions
To provide memory addresses.
During Sector-Erase A
MS
-A
12
address lines will select the sector.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide 5.0V supply (4.5-5.5V)
Unconnected pins.
T2.2 1147
CE#
OE#
WE#
V
DD
V
SS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
1. A
MS
= Most significant address
A
MS
= A
16
for SST39SF010A, A
17
for SST39SF020A, and A
18
for SST39SF040
TABLE 3: O
PERATION
M
ODES
S
ELECTION
Mode
Read
Program
Erase
Standby
Write Inhibit
Product Identification
Software Mode
V
IL
V
IL
V
IH
See Table 4
T3.3 1147
CE#
V
IL
V
IL
V
IL
V
IH
X
X
OE#
V
IL
V
IH
V
IH
X
V
IL
X
WE#
V
IH
V
IL
V
IL
X
X
V
IH
DQ
D
OUT
D
IN
X
1
High Z
High Z/ D
OUT
High Z/ D
OUT
Address
A
IN
A
IN
Sector address,
XXH for Chip-Erase
X
X
X
1. X can be V
IL
or V
IH
, but no other value.
©2003 Silicon Storage Technology, Inc.
S71147-06-000
8/04
6
SST [ SILICON STORAGE TECHNOLOGY, INC ]
