16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
Data Protection
The SST39VF168x provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
RHR
is
required after RST# is driven high before a valid Read can
take place (see Figure 15).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF168x provide the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. These devices are shipped with the Software
Data Protection permanently enabled. See Table 6 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within T
RC.
Hardware Block Protection
The SST39VF1682 supports top hardware block protec-
tion, which protects the top 64 KByte block of the device.
The SST39VF1681 supports bottom hardware block pro-
tection, which protects the bottom 64 KByte block of the
device. The Boot Block address ranges are described in
the 64 KByte when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
TABLE 2: B
OOT
B
LOCK
A
DDRESS
R
ANGES
Product
Bottom Boot Block
SST39VF1681
Top Boot Block
SST39VF1682
1F0000H-1FFFFFH
T2.1 1243
Address Range
000000H-00FFFFH
Common Flash Memory Interface (CFI)
The SST39VF168x also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as product ID entry command with 98H
(CFI Query command) to address AAAH in the last byte
sequence. Once the device enters the CFI Query mode, the
system can read CFI data at the addresses given in Tables
7 through 9. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
