3 Mbit LPC Flash
SST49LF030A
EOL Product Data Sheet
TABLE 5: LPC Read Cycle
Clock
Cycle
0-1
Field
Name
START
Field Contents
LAD[3:0]
1
0000
LAD[3:0]
Direction
IN
Comments
LFRAME# must be active (low) for the part to respond. Only the
last start field (before LFRAME# transitions high) should be rec-
ognized.
Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.
Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved.
Address Phase for Memory Cycle. LPC protocol supports a 32-
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble fist. See Table
address range.
In this clock cycle, the host has driven the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
The SST49LF030A takes control of the bus during this cycle
The SST49LF030A outputs the value 0000b indicating that data
will be available during the next clock cycle.
This field is the least-significant nibble of the data byte.
This field is the most-significant nibble of the data byte.
In this clock cycle, the SST49LF030A has driven the bus to all
1s and then floats the bus. This is the first part of the bus “turn-
around cycle.”
The host takes control of the bus during this cycle
T5.0 1234
2
3-10
CYCTYPE
+ DIR
ADDRESS
010X
YYYY
IN
IN
11
12
13
14
15
16
TAR0
TAR1
SYNC
DATA
DATA
TAR0
1111
1111 (float)
0000
ZZZZ
ZZZZ
1111
IN
then Float
Float
then OUT
OUT
OUT
OUT
OUT
then Float
Float
then IN
17
TAR1
1111 (float)
1. Field contents are valid on the rising edge of the present clock cycle.
CE#
0
LCLK
LFRAME#
Start
CYCTYPE
+
DIR
010Xb
Address
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
Load Address in 8 Clocks
A[7:4]
A[3:0]
TAR0
1111b
TAR1
Tri-State
Sync
0000b
D[3:0]
Data
D[7:4]
TAR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
LAD[3:0]
0000b
1 Clock 1 Clock
2 Clocks
1 Clock Data Out 2 Clocks
1234 F04.1
FIGURE 5: LPC Read Cycle Waveform
©2005 Silicon Storage Technology, Inc.
S71234-03-EOL
5/06
12
SST [ SILICON STORAGE TECHNOLOGY, INC ]
