3 Mbit LPC Flash
SST49LF030A
EOL Product Data Sheet
General Purpose Inputs Register
JEDEC ID Registers
The GPI_REG (General Purpose Inputs Register) passes
the state of GPI[4:0] pins at power-up on the
SST49LF030A. It is recommended that the GPI[4:0] pins
be in the desired state before LFRAME# is brought low for
the beginning of the next bus cycle, and remain in that state
until the end of the cycle. There is no default value since
this is a pass-through register. See the General Purpose
Inputs Register table for the GPI_REG bits and function,
and Table 9 for memory address locations for its respective
device strapping.
The JEDEC ID registers identify the device as
SST49LF030A and manufacturer as SST in LPC mode.
See Table 9 for memory address locations for its respective
JEDEC ID location.
TABLE 9: Memory Map Register Addresses1
JEDEC ID
Device #
Hardware Strapping ID[3:0]
GPI_REG
FFBC 0100H
FFB4 0100H
FFAC 0100H
FFA4 0100H
FF9C 0100H
FF94 0100H
FF8C 0100H
FF84 0100H
FF3C 0100H
FF34 0100H
FF2C 0100H
FF24 0100H
FF1C 0100H
FF14 0100H
FF0C 0100H
FF04 0100H
Manufacturer
FFBC 0000H
FFB4 0000H
FFAC 0000H
FFA4 0000H
FF9C 0000H
FF94 0000H
FF8C 0000H
FF84 0000H
FF3C 0000H
FF34 0000H
FF2C 0000H
FF24 0000H
FF1C 0000H
FF14 0000H
FF0C 0000H
FF04 0000H
Device
0 (Boot device)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FFBC 0001H
FFB4 0001H
FFAC 0001H
FFA4 0001H
FF9C 0001H
FF94 0001H
FF8C 0001H
FF84 0001H
FF3C 0001H
FF34 0001H
FF2C 0001H
FF24 0001H
FF1C 0001H
FF14 0001H
FF0C 0001H
FF04 0001H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T9.0 1234
1. Operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map.
©2005 Silicon Storage Technology, Inc.
S71234-03-EOL
5/06
16
SST [ SILICON STORAGE TECHNOLOGY, INC ]
