FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
7.0 WATCHDOG TIMER
The device offers a programmable Watchdog Timer (WDT)
for fail safe protection against software deadlock and auto-
matic recovery.
To protect the system against software deadlock, the user
software must refresh the WDT within a user-defined time
period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE=
1). The software can be designed such that the WDT times
out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as
its time base. So strictly speaking, it is a watchdog counter
rather than a watchdog timer. The WDT register will incre-
ment every 344,064 crystal clocks. The upper 8-bits of the
time base register (WDTD) are used as the reload register
of the WDT.
The WDTS flag bit is set by WDT overflow and is not
changed by WDT reset. User software can clear WDTS by
writing “1” to it.
(WDTC and WDTD) control watchdog timer operation.
During idle mode, WDT operation is temporarily sus-
pended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDTD) * 344064 * 1/f
CLK (XTAL1)
where WDTD is the value loaded into the WDTD register
and f
OSC
is the oscillator frequency.
CLK (XTAL1)
Counter
344064
clks
WDT Upper Byte
WDT Reset
Internal Reset
Ext. RST
WDTC
WDTD
1273 F19.0
FIGURE
7-1: Block Diagram of Programmable Watchdog Timer
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
45
SST [ SILICON STORAGE TECHNOLOGY, INC ]
