FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
VDD
VDD
P0
RST
EA#
RST
IDD
VDD
VDD
P0
EA#
VDD
IDD
VDD
SST89x516RDx
CLOCK
SIGNAL
(NC)
XTAL2
XTAL1
VSS
1273 F41.0
SST89x5xxRDx
(NC)
XTAL2
XTAL1
VSS
1273 F42.0
All other pins disconnected
All other pins disconnected
FIGURE 14-12: I
DD
Test Condition,
Idle Mode
FIGURE 14-13: I
DD
Test Condition,
Power-down Mode
TABLE 14-11: Flash Memory Programming/
Verification Parameters
1
Parameter
2
Chip-Erase Time
Block-Erase Time
Sector-Erase Time
Byte-Program Time
3
Select-Block Program Time
Re-map or Security bit Program Time
Max
150
100
30
50
500
80
Units
ms
ms
ms
µs
ns
µs
T14-11.1 1273
1. For IAP operations, the program execution overhead
must be added to the above timing parameters.
2. Program and Erase times will scale inversely proportional
to programming clock frequency.
3. Each byte must be erased before programming.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
76
SST [ SILICON STORAGE TECHNOLOGY, INC ]
