ST6200C/ST6201C/ST6203C
MEMORY MAP
(Cont’d)
Table 2. Hardware Register Map
Address
080h
to 083h
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
to 0D7h
0D8h
0D9h
to 0FEh
0FFh
CPU
A
Watchdog
Timer
WDGR
ADC
ADR
ADCR
PSCR
TCR
TSCR
I/O Ports
ORA
2)
ORB
2)
CPU
ROM
IOR
DRWR
I/O Ports
DDRA
2)
DDRB
2)
Block
CPU
I/O Ports
Register
Label
X,Y,V,W
DRA
1) 2) 3)
DRB
1) 2) 3)
Register Name
X,Y index registers
V,W short direct registers
Port A Data Register
Port B Data Register
Reserved (2 Bytes)
Port A Direction Register
Port B Direction Register
Reserved (2 Bytes)
Interrupt Option Register
Data ROM Window register
Reserved (2 Bytes)
Port A Option Register
Port B Option Register
Reserved (2 bytes)
A/D Converter Data Register
A/D Converter Control Register
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
Reserved (3 Bytes)
Watchdog Register
Reserved (38 Bytes)
Accumulator
xxh
R/W
0FEh
R/W
xxh
40h
7Fh
0FFh
00h
Read-only
Ro/Wo
R/W
R/W
R/W
00h
00h
R/W
R/W
xxh
xxh
Write-only
Write-only
00h
00h
R/W
R/W
Reset
Status
xxh
00h
00h
Remarks
R/W
R/W
R/W
Timer 1
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to
Section 7 "I/O PORTS" on page 36
for more details).
4. Depending on device. See device summary on page 1.
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