STM8S105xx
Electrical characteristics
Figure 39: Typical NRST pull-up current vs V
DD
@ 4 temperatures
The reset network shown inthe following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below the V
IL
max. level specified
in the I/O port pin characteristics section. Otherwise the reset is not taken into account
internally.
Figure 40: Recommended reset pin protection
VDD
STM8
RPU
External
reset
circuit
0.01 μF
(optional)
NRST
Filter
Internal reset
10.3.9
SPI serial peripheral interface
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, f
MASTER
frequency and V
DD
supply voltage conditions.
t
MASTER
= 1/f
MASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
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