uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate External Chip Select
(ECS1-ECS2), routed to Port D.
Although External Chip Select (ECS1-ECS2) can
be produced by any Output Macrocell (OMC),
these External Chip Select (ECS1-ECS2) on Port
D do not consume any Output Macrocells (OMC).
As shown in Figure
the CPLD has the following
blocks:
– 20 Input Macrocells (IMC)
– 16 Output Macrocells (OMC)
– Macrocell Allocator
– Product Term Allocator
Figure 60. Macrocell and I/O Port
PLD INPUT BUS
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
TO OTHER I/O PORTS
–
AND Array capable of generating up to 137
product terms
– Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD Module internal
data bus and can be directly accessed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
CPLD MACROCELLS
PT PRESET
PRODUCT TERM
ALLOCATOR
MCU DATA IN
MCU LOAD
DATA
LOAD
CONTROL
I/O PORTS
LATCHED
ADDRESS OUT
DATA
WR
I/O PIN
D
Q
MUX
AND ARRAY
UP TO 10
PRODUCT TERMS
MACROCELL
OUT TO
MCU
CPLD OUTPUT
PR DI LD
PT
CLOCK
D/T
MUX
Q
COMB.
/REG
SELECT
CPLD
OUTPUT
MACROCELL
TO
I/O PORT
ALLOC.
WR
PT CLEAR
PDR
INPUT
SELECT
PLD INPUT BUS
GLOBAL
CLOCK
CLOCK
SELECT
D/T/JK FF
SELECT
CK
CL
MUX
POLARITY
SELECT
D
Q
DIR
REG.
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
INPUT MACROCELLS
MUX
Q D
PT INPUT LATCH GATE/CLOCK
MUX
ALE
Q D
G
AI06602
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STMICROELECTRONICS [ STMICROELECTRONICS ]
