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S24022SBT 参数 Datasheet PDF下载

S24022SBT图片预览
型号: S24022SBT
PDF下载: 下载PDF文件 查看货源
内容描述: 精密复位控制器和4K I2C存储器既RESET和RESET输出 [Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs]
分类和应用: 存储控制器
文件页数/大小: 14 页 / 157 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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S24042/S24043
Sequential READ
Sequential READs can be initiated as either a current
address READ or random access READ. The first word is
transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, the master now responds with an ACKnowledge,
indicating that it requires additional data from the
S24042/43. The S24042/43 continues to output data for
each ACKnowledge received. The master terminates the
sequential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.
During a sequential read operation, the internal address
counter is automatically incremented with each acknowl-
edge signal. For read operations, all address bits are
incremented, allowing the entire array to be read using a
single read command. After a count of the last memory
address, the address counter will ‘roll-over’ and the
memory will continue to output data. See Figure 9 for the
address, acknowledge and data transfer sequence.
Acknowledges from 24042/43
Acknowledge from
Master Receiver
Lack of
Acknowledge from
Master Receiver
SDA Bus
Activity
1 0 1 0
S
T Device
A Type
R Address
T
X X
A R
W
8
A
C
Word Address
K
A A A A A A A A
7 6 5 4 3 2 1 0
A
C
K
R
X X
W
8
A
A
C
K
A
First Data Byte
C
K
D D D D D D D D
7 6 5 4 3 2 1 0
Last Data Byte
A
8
0
1 0 1 0
S
T Device
A
Type
R Address
T
1
D D D D D D D D
7 6 5 4 3 2 1 0
1
S
T
O
P
Read/Write
0= Write
Read/Write
1= Read
Slave Address
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Slave Address
Master Requests
Data from Slave
Slave sends
Data to Master
Lack of ACK (low)
determines last
data byte to be read
Slave sends
Data to Master
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
2011 T fig09 2.0
Shading Denotes
24042/43
SDA Output Active
FIGURE 9. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
2011 2.1 8/2/00
SUMMIT MICROELECTRONICS, Inc.
8