S4242/S42WD42/S4261/S42WD61
Watchdog Timer Operation
VTRIP,thewatchdogwillcontinuetobeheldinaresetstate
The S42WD42/S42WD61 has a watchdog timer with a for the duration of tPURST. After tPURST, the timer will be
nominal timeout period of 1.6 seconds. Whenever the released and begin counting.
watchdog times out it will generate a reset output on both
If either reset input is asserted the watchdog timer will be
RESET# and RESET. The watchdog timer will reset to t0
reset and remain in the reset condition until either tPURST
whenever the S42WD42/S42WD61 issues an ACKnowl-
has expired or the reset input is released, whichever is
edge. Therefore, thehostsystemwillneedtoissueastart
longer.
condition, followed by a valid address and command. It
can be a normal command as in the sequence of reading If the watchdog times out and no action is taken by the
or writing to the memory, or it can be a dummy command host, the S42xxx will drive the reset outputs active for the
issued solely for the purpose of resetting the watchdog duration of tPURST at which point it will release the outputs
timer. Refer to Figure 17 for detailed sequence of opera- andbeginthewatchdogtimeragain.RefertoFigure18for
tions.
detailed sequence of operations.
The watchdog timer will be held in the reset state during
power-onwhileVCC islessthanVTRIP.OnceVCC exceeds
S
T
A
R
T
S
S
T
A
R
T
T
A
R
T
S
T
O
P
S
T
O
P
S
T
O
P
R
R
R
1 0 1 0 x x x
1 0 1 0 x x x
W
W
1 0 1 0 x x x
W
SCL and SDA Idle
SCL and SDA Idle
A
C
K
A
C
K
A
C
K
tPURST
ACK response from S42xxx
Resets The Watchdog Timer
RESET#
t < 1.6sec
t > 1.6sec
t0
t0
t0
2025 T fig17 2.0
FIGURE 17. SEQUENCE ONE
S
T
A
R
T
S
T
A
R
S
T
O
P
S
T
O
P
R
R
1 0 1 0 x x x
W
T
1 0 1 0 x x x
W
SCL and SDA Idle
SCL and SDA Idle
A
C
K
A
C
K
No Affect On tPURST
Watchdog Timer t0
tPURST
RESET#
t > 1.6sec
t > 1.6sec
t0
t0
2025 T fig18 2.0
FIGURE 18. SEQUENCE TWO
2025 6.0 4/17/00
13
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
