SMH4044
Preliminary
V
CC
&
HST_3V_MON
V
TRIP
V
RVALID
LOCAL_PCI_RST#
BD_SEL1# &
BD_SEL2#
VGATE3 &
VGATE5
t
HSE
t
SLEW
V
OHVG
DRVREN#
CARD_3V_MON &
CARD_5V_MON
V
TRIP
t
PURST
HEALTHY#
SGNL_VLD#
2057 Fig01
Figure 1. Card Insertion Timing Diagram
Symbol
t
VTPD
t
VTR
t
PRLPR
t
SLEW
Parameter
V
TRIP
to power down delay
V
TRIP
to reset output delay
PCI_RST# to LOCAL_PCI_RST#
Slew rate
25ms configuration
t
HSE
BD_SEL# to power on delay
50ms configuration
100ms configuration
200ms configuration
25ms configuration
t
PURST
RESET pulse width
50ms configuration
100ms configuration
200ms configuration
0.8s configuration
t
WD
t
GLITCH
t
OCF
t
OCVG
t
CBTC
Watchdog timer duration
Glitch rejection pulse width
Overcurrent to FAULT# output
Overcurrent to gate off
Circuit breaker time constant
Operating
Table 1. Card Insertion Timing
10
2057 1.x 8/16/01
SUMMIT MICROELECTRONICS, Inc.
Conditions
Min.
Typ.
1
1
0.1
Max.
5
5
1
250
30
60
120
240
30
60
120
240
0.96
1.92
3.84
40
Units
µs
µs
µs
V/s
ms
ms
ms
ms
ms
ms
ms
ms
s
s
s
ns
µs
µs
µs
2057 Table01
20
40
80
160
20
40
80
160
0.64
1.28
2.56
25
50
100
200
25
50
100
200
0.8
1.6
3.2
1
1
16
1.6s configuration
3.2s configuration
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
