SMH4812
Preliminary
ENPG (14)
The ENPG input controls the PG# output. When ENPG is
pulled low the PG# output is immediately placed in a high
impedance state. If ENPG is driven high then the PG#
output will immediately be driven low.
PG# (15)
PG# is an open-drain, active-low output with no internal
pull-up resistor. It can be used to switch a load or enable
a DC/DC converter. PG# is enabled immediately after
VGATE reaches V
DD
– V
GT
and the DRAIN SENSE
voltage is less than 2.5V. Voltage on these pins cannot
exceed 12V, as referenced to V
SS.
V
DD
(16)
V
DD
is the positive supply connection. An internal shunt
regulator connected between V
DD
and V
SS
develops ap-
proximately 12V that supplies the SMH4812. A resistor
must be placed in series with the V
DD
pin to limit the
regulator current (RD in the application illustrations).
V
SS
(8)
V
SS
is connected to the negative side of the supply.
4
2055 4.1 03/27/09
SUMMIT MICROELECTRONICS, Inc.
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
