HV6506
Functional Block Diagram
V
PP
Polarity
Latch Enable
V
DD
Data Input
Latch
HV
OUT
1
Clock
32-Bit
Shift
Register
Latch
HV
OUT
2
DIR
(Outputs 3 to 30
not shown)
HV
OUT
31
Latch
Data Out
Latch
HV
OUT
32
BP
OUT
GND
Function Table
Inputs
Function
Load S/R
Load latches
Data
H or L
X
X
All high
H
L
All low
H
L
L
Transparent
Mode
H
L
H
R/L Shift
X
X
CLK
↑
H or L
H or L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
LE
L
L
L
H
H
H
H
H
H
H
H
X
X
POL
H
H
L
L
H
H
L
H
H
L
L
X
X
DIR
X
X
X
X
X
X
X
X
X
X
X
H
L
Shift Reg
1
2…32
H or L
*
*
H
L
H
L
L
H
L
H
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
Outputs
HV Outputs
1
*
*
*
H
H
L
L
H
L
L
H
*
*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
*…*
Data Out
2…32
*
*
*
*
*
*
*
*
*
*
*
Q32
Q1
BP
OUT
*
H
H
L
L
H
H
L
H
H
L
L
12
Qn
→
Qn+1
Qn
→
Qn-1
Notes:
H = high level, L = low level, X = irrelevant,
↑
= low-to-high transition.
*
= dependent on previous stage’s state before the last CLK or last LE high.
12-135
SUPERTEX [ Supertex, Inc ]
