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HV7224PG 参数 Datasheet PDF下载

HV7224PG图片预览
型号: HV7224PG
PDF下载: 下载PDF文件 查看货源
内容描述: 40通道对称行驱动器 [40-Channel Symmetric Row Driver]
分类和应用: 显示驱动器驱动程序和接口接口集成电路
文件页数/大小: 7 页 / 467 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV7224
Electrical Characteristics
(over recommended operating conditions of V
DD
= 5V, V
PP
= 240V, and T
A
= 25°C unless noted)
DC Characteristics
Symbol
I
DD
I
PP
I
DDQ
V
OH
V
OL
I
IH
I
IL
I
SAT
V
DD
supply current
High voltage supply current
Quiescent V
DD
supply current
High-level output
HV
OUT
Data out
Low-level output
HV
OUT
Data out
High-level logic input current
Low-level logic input current
Saturation current HV
OUT
P-Ch
N-Ch
Note:
1. Only one output can be turned on at a time.
Parameter
Min
Max
10
2.0
4.0
100
Units
mA
mA
mA
µA
V
V
Conditions
f
CLK
= 3MHz
Outputs low or High-Z
One Output High
1
All V
IN
= GND or V
DD
I
O
= -70mA
I
O
= -100µA
I
O
= 70mA
I
O
= 100µA
V
IH
= V
DD
V
IL
= 0V
190
4.5
50
0.5
1.0
-1.0
-80
75
V
V
µA
µA
mA
mA
AC Characteristics
Symbol
f
CLK
t
W (H/L)
t
SUD
t
HD
t
SUC
t
SUE
t
HC
t
HE
t
DHL*
t
DLH*
t
ONF
t
ONR
t
POW
t
OEW
Parameter
Clock frequency
Pulse width - clock high or low
Data set-up time before clock rises
Data hold time after clock rises
HV
OUT
delay from clock rises (Hi-Z to H or L)
HV
OUT
delay from Output Enable falls
HV
OUT
delay from clock rises (H or L to Hi-Z)
HV
OUT
delay from Output Enable rises
Delay time clock to data output falls
Delay time clock to data output rises
HV
OUT
fall time
HV
OUT
rise time
POL pulse width
Output Enable pulse width
Slew rate, V
PP
or GND
3.0
3.0
45
150
50
50
1.0
600
2.0
600
250
250
2.0
2.0
Min
Max
3.0
Units
MHz
ns
ns
ns
µs
ns
µs
ns
ns
ns
µs
µs
µs
µs
V/µs
One active output driving
4.7nF load
C
L
= 330pF // R
L
= 10kΩ
C
L
= 330pF // R
L
= 10kΩ
C
L
= 330pF // R
L
= 10kΩ
C
L
= 330pF // R
L
= 10kΩ
C
L
= 15pF
C
L
= 15pF
C
L
= 330pF // R
L
= 10kΩ
C
L
= 330pF // R
L
= 10kΩ
Conditions
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to t
WH
. Therefore the delay is measured from the trailing edge of the clock.
2