HV7224
Functional Block Diagram
V
PP
OE
Polarity
V
DD
LT
P
HV
OUT
1
D
IOA
N
SHIFT
CLK
S/R
DIR
LT
HV
OUT
2
LT
D
IOB
HV
OUT
40
GND
LT = Level Translator
Function Table
I/O Relations
CLK
O/P HIGH
O/P OFF
O/P LOW
O/P OFF
X
X
X
X
DIR
X
X
X
X
Inputs
S/R Data
H
L
H
X
POL
H
X
L
X
OE
L
L
L
H
HV Outputs
H
HIGH-Z
L
All O/P HIGH-Z
Notes:
H = logic high level, L = logic low level, X = irrelevant
Data input (DR
IO
) loaded on the low-to-high transistion of the clock.
Only one active output can be set at a time.
Output Sequence Operation Table
DIR
L
H
L
H
Shift
L
L
H
H
Data Reset In Data Reset Out
DR
IOB
DR
IOA
DR
IOB
DR
IOA
DR
IOA1
DR
IOB2
DR
IOA1
DR
IOB2
HV
OUT
# Sequence
40
→
1
1
→
40
20
→
1
→
40
→
21
21
→
40
→
1
→
20
Direction*
Option (See pin-out on P. 12-158)
A
A
B
B
* Reference to package outline or chip layout drawing.
1.DR
IOA
is DR
IOB
delayed by 40 clock pulses.
2. DR
IOB
is DR
IOA
delayed by 40 clock pulses.
5
SUPERTEX [ Supertex, Inc ]
