SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
6. Timer 0 and Timer 1
The SM39R08A5 has two 16-bit timer/counter registers: Timer 0 and Timer 1. All can be configured for counter or timer
operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 12 machine cycles, which means that it
counts up after every 12 periods of the clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic
TL0
TH0
TL1
TH1
TMOD
TCON
AUX
Description
Timer 0 , low byte
Timer 0 , high byte
Timer 1 , low byte
Timer 1 , high byte
Timer Mode Control
Timer/Counter Control
Auxiliary register
Direct
8Ah
8Ch
8Bh
8Dh
89h
88h
91h
Bit 7 Bit 6 Bit 5
Timer 0 and 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
00h
00h
00h
00h
00h
00h
00H
GATE
TF1
BRGS
C/T
TR1
-
M1
TF0
-
TL0[7:0]
TH0[7:0]
TL1[7:0]
TH1[7:0]
M0 GATE
TR0
IE1
PTS[1:0]
C/T
M1
IT1
IE0
PINTS[1:0]
M0
IT0
DPS
6.1. Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
3
GATE
2
1
C/T
M1
Timer 0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON register), a
counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is performed,
when cleared to 0, the corresponding register will function as a timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1
M0
Mode
Function
0
0
Mode0
13-bit counter/timer, with 5 lower bits in TL0 or TL1
register and 8 bits in TH0 or TH1 register (for Timer 0
and Timer 1, respectively). The 3 high order bits of
TL0 and TL1 are hold at zero.
0
1
Mode1
16-bit counter/timer.
1
0
Mode2
8 -bit auto-reload counter/timer. The reload value is
kept in TH0 or TH1, while TL0 or TL1 is incremented
every machine cycle. When TLx overflows, a value
from THx is copied to TLx.
1
1
Mode3
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts
as two independent 8 bit timers / counters.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 23 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
